Frequency dividing circuit

Abstract

PURPOSE:To extend an operating frequency range and a variable range by controlling a prescaler only in one frequency division cycle by a terminal count signal of a preset counter in a frequency dividing circuit consisting of the prescaler consisting of plural D FFs and the preset counter. CONSTITUTION:Normally, a prescaler 100 supplies an N-divided clock to a preset counter (PSC) 11. The PSC 11 counts the N-divided clock, and the PSC 11 sends a terminal count signal TC to the prescaler 100 when terminating prescribed counting. The prescaler 100 divides the frequency by one of preliminarily set N-2N-1 in on frequency division cycle after reception of the signal TC. Then, the PSC 11 divides the frequency of the N-divided clock by K (>=0), and thereafter, the prescaler divides the frequency by J (N<=J<=2N-1) only in one frequency division cycle after the N-division operation. Thus, a frequency division number M obtained by the PSC 11 and the prescaler 100 is J+K.N and frequency division is continuously performed from N-division.

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Patent Citations (2)

    Publication numberPublication dateAssigneeTitle
    JP-S52108762-ASeptember 12, 1977Toshiba CorpFrequency division circuit
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Cited By (3)

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    US-5787344-AJuly 28, 1998Scheinert; StefanArrangements of base transceiver stations of an area-covering network
    US-6263200-B1July 17, 2001Nec CorporationRadio terminal apparatus equipped with battery power saving function, and mobile communication system using the same
    US-RE37820-EAugust 13, 2002Littlefeet, Inc.Arrangements of base transceiver stations of an area-covering network